Thank you for your help in linear voltage stabilizer is mandatory is in the assumptions of my project. asc file and the schematic of my power supply. Prevent the voltage oscilations on the transformer (especially at low duty cycles). Achieve good voltage regulation by changing the duty cycle.ģ. Achieve better efficiency (I was hoping to get more than 85% or 88% at full load).Ģ. I am stuck with this problem and cannot think of any other solution how to:ġ. And that affects efficiency for lower output voltage values. However, with the RC snubber (9k, 100p) I cannot recieve good voltage regulation on the LC filter (on the secondary side of the transformer) because the turn off time is very long (I think due to lower current value) and that affects the duration of dead time (it is very well seen at low duty cycles ~ 10%). And then the maximum efficiency was around 75% at full load. I think the main problem with the low efficiency is that I have implemented an RC snubber circuit on the primary side of the transformer to prevent the voltage oscillations when turning transistors OFF.Īnd I know why there is a lot of power dissipation, so I changed the values by increasing resistance up to 9k Ohms and capacitance to 100 pF. Output power: 125 W (maximum) (I know Full-Bridge topology isn't the best fit for this power level)

When I was making measurements I discovered that the maximum efficiency of my power supply is around 30% at full load. Hello, I am designing full-bridge SMPS with a linear voltage stabilizer in LTspice.

Smps full bridge